![]() The current board is using the Xilinx XC95144XL-10TQG100C CPLD to implement the control logic but that's just because we at GW have a few trays of them from a cancelled project. CPU speed is selectable, either 20 MHz or 25 MHz. The accelerator trickles out these writes from the fast CPU to the slower PDS bus while the fast CPU gets to continue executing from RAM or ROM memory on the card. This lets the accelerated CPU write to video/sound memory up to twice in a row with 0 wait states. ![]() ![]() In order to achieve the requisite 3x speedup on graphics performance, I have implemented a longword posted write buffer. The Macintosh SE ROM is also reproduced on the board in two 512kx8 70ns flash ROMs. The card has 4 MB of legacy 60ns DRAM onboard which can be accessed with 0 wait states at 25 MHz. Therefore I have employed an MC68HC000 running at up to 25 MHz instead of an '030. My aim with this card is to achieve a speedup of 3x or so while maintaining the greatest degree of compatibility with applications. I'm the principal designer and Garrett is the codesigner and he manufactures our boards. As usual with my gizmos, this is a collaboration with Garrett Fellers of Garrett's Workshop. I wanted to post about my new design for a 25 MHz 68HC000-based Macintosh SE accelerator.
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